D12320VF25IV Datasheet, PDF (397/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
Port 2 Data Register (P2DR)
Bit
:
Initial value :
R/W
:
7
P27DR
0
R/W
6
P26DR
0
R/W
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
0
P20DR
0
R/W
P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P2₇ to P2₀).
P2DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port 2 Register (PORT2)
Bit
:
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
Initial value : —^*
—^*
—^*
—^*
—^*
—^*
—^*
—^*
R/W
:R
R
R
R
R
R
R
R
Note: * Determined by state of pins P27 to P20.
PORT2 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 2 pins (P2₇ to P2₀) must always be performed on P2DR.
If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read. If a port 2
read is performed while P2DDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORT2 contents are determined by the pin states, as
P2DDR and P2DR are initialized. PORT2 retains its prior state in software standby mode.
Rev.6.00 Sep. 27, 2007 Page 365 of 1268
REJ09B0220-0600