EP4SE360F35I4 Datasheet, PDF (98/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

4–18
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Figure 4–10. 9-Bit Independent Multiplier Mode Shown for a Half Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
9
dataa_0[8..0]
9
datab_0[8..0]
9
dataa_1[8..0]
9
datab_1[8..0]
9
dataa_2[8..0]
9
datab_2[8..0]
9
dataa_3[8..0]
9
datab_3[8..0]
18
result_0[ ]
18
result_1[ ]
18
result_2[ ]
18
result_3[ ]
Half-DSP Block
The multiplier operands can accept signed integers, unsigned integers, or a
combination of both. You can change the signa and signb signals dynamically and
can register the signals in the DSP block. Additionally, the multiplier inputs and
results can be registered independently. You can use the pipeline registers within the
DSP block to pipeline the multiplier result, increasing the performance of the DSP
block.
1 The rounding and saturation logic unit is supported for 18-bit independent multiplier
mode only.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation