EP4SE360F35I4 Datasheet, PDF (199/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
6–25
A pair of RUP and RDN pins are available in a given I/O bank and are shared for
series- and parallel-calibrated termination. The RUP and RDN pins share the same V_CCIO
and GND, respectively, with the I/O bank where they are located. The RUP and RDN
pins are dual-purpose I/Os and function as regular I/Os if you do not use the
calibration circuit.
For calibration, the connections are as follows:
■ The RUP pin is connected to V_CCIO through an external 25- ±1% or 50- ±1%
resistor for an on-chip series termination value of 25-or 50-, respectively.
■ The RDN pin is connected to GND through an external 25- ±1% or 50- ±1%
resistor for an on-chip series termination value of 25-or 50-, respectively.
For on-chip parallel termination, the connections are as follows:
■ The RUP pin is connected to V_CCIO through an external 50- ±1% resistor.
■ The RDN pin is connected to GND through an external 50- ±1% resistor.
On-Chip Series (R_S) Termination Without Calibration
Stratix IV devices support driver-impedance matching to provide the I/O driver with
controlled output impedance that closely matches the impedance of the transmission
line. As a result, you can significantly reduce reflections. Stratix IV devices support
on-chip series termination for single-ended I/O standards (Figure 6–18).
The R_S shown in Figure 6–18 is the intrinsic impedance of the output transistors.
Typical R_S values are 25  and 50 . When you select matching impedance, current
strength is no longer selectable.
Figure 6–18. On-Chip Series Termination Without Calibration
Stratix IV Driver
Series Termination
V_CCIO
Receiving
Device
R_S
Z_O = 50 Ω
R_S
GND
To use on-chip termination for the SSTL Class I standard, you must select the 50-
on-chip series termination setting, thus eliminating the external 25- R_S (to match
the 50- transmission line). For the SSTL Class II standard, you must select the 25-
on-chip series termination setting (to match the 50- transmission line and the
near-end external 50- pull-up to V_TT).
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1