EP4SE360F35I4 Datasheet, PDF (287/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
8–7
LVDS Channels
Table 8–5. LVDS Channels Supported in Stratix IV GX Device Row I/O Banks ⁽¹⁾, ⁽²⁾, ⁽³⁾ (Part 2 of 2)
Device
780-Pin
FineLine BGA
1152-Pin
FineLine BGA
1152-Pin
FineLine BGA
(4)
1517-Pin
FineLine BGA
1760-Pin
FineLine BGA
1932-Pin
FineLine BGA
EP4SGX360
— ⁽⁵⁾
44 Rx or eTx + 44 Rx or eTx + 88 Rx or eTx + 88 Rx or eTx + 98 Rx or eTx +
44 Tx or eTx 44 Tx or eTx 88 Tx or eTx 88 Tx or eTx 98 Tx or eTx
EP4SGX530
—
—
44 Rx or eTx + 88 Rx or eTx + 88 Rx or eTx + 98 Rx or eTx +
44 Tx or eTx ⁽⁶⁾ 88 Tx or eTx ⁽⁷⁾ 88 Tx or eTx 98 Tx or eTx
Notes to Table 8–5:
(1) Rx = true LVDS input buffers with OCT R_D, Tx = true LVDS output buffers, eTx = emulated LVDS output buffers (either LVDS_E_1R or
LVDS_E_3R).
(2) The LVDS Rx and Tx channels are equally divided between the left and right sides of the device, except for the devices in the 780-pin Fineline
BGA. These devices have the LVDS Rx and Tx located on the left side of the device.
(3) The LVDS channel count does not include dedicated clock input pins.
(4) This package supports PMA-only transceiver channels.
(5) EP4SGX290 and EP4SGX360 devices are offered in the H780 package instead of the F780 package.
(6) EP4SGX530 devices are offered in the H1152 package instead of the F1152 package.
(7) EP4SGX530 devices are offered in the H1517 package instead of the F1517 package.
Table 8–6. LVDS Channels Supported in Stratix IV GX Device Column I/O Banks ⁽¹⁾, ⁽²⁾, ⁽³⁾
Device
780-Pin
FineLine BGA
1152-Pin
FineLine BGA
1152-Pin
FineLine BGA
(4)
1517-Pin
FineLine BGA
1760-Pin
FineLine BGA
1932-Pin
FineLine BGA
EP4SGX70
64 Rx or eTx +
64 eTx
—
64 Rx or eTx +
64 eTx
—
—
—
EP4SGX110
64 Rx or eTx +
64 eTx
64 Rx or eTx +
64 eTx
64 Rx or eTx +
64 eTx
—
—
—
EP4SGX180
64 Rx or eTx +
64 eTx
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
—
—
EP4SGX230
64 Rx or eTx +
64 eTx
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
—
—
EP4SGX290
72 Rx or eTx +
72 eTx ⁽⁵⁾
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
96 Rx or eTx + 128 Rx or eTx + 128 Rx or eTx +
96 eTx
128 eTx
128 eTx ⁽⁸⁾
EP4SGX360
72 Rx or eTx +
72 eTx ⁽⁵⁾
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
96 Rx or eTx + 128 Rx or eTx + 128 Rx or eTx +
96 eTx
128 eTx
128 eTx ⁽⁸⁾
EP4SGX530
—
—
96 Rx or eTx + 96 Rx or eTx + 128 Rx or eTx + 128 Rx or eTx +
96 eTx ⁽⁶⁾
96 eTx ⁽⁷⁾
128 eTx
128 eTx
Notes to Table 8–6:
(1) Rx = true LVDS input buffers without OCT R_D, eTx = emulated LVDS output buffers (either LVDS_E_1R or LVDS_E_3R).
(2) The LVDS Rx and Tx channels are equally divided between the left and right sides of the device.
(3) The LVDS channel count does not include dedicated clock input pins.
(4) This package supports PMA-only transceiver channels.
(5) EP4SGX290 and EP4SGX360 devices are offered in the H780 package instead of the F780 package.
(6) EP4SGX530 devices are offered in the H1152 package instead of the F1152 package.
(7) EP4SGX530 devices are offered in the H1517 package instead of the F1517 package.
(8) The Quartus II software version 9.0 does not support EP4SGX290 and EP4SGX360 devices in the 1932-Pin FineLine BGA package. These
devices will be supported in a future release of the Quartus II software.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1