EP4SE360F35I4 Datasheet, PDF (121/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
5–5
Clock Networks in Stratix IV Devices
Figure 5–3. RCLK Networks (EP4S40G2, EP4S100G2, EP4SGX180, and EP4SGX230 Devices) ⁽¹⁾
CLK[12..15]
T1 T2
RCLK[54..63] RCLK[44..53]
RCLK[0..5]
L2
CLK[0..3]
L3
RCLK[6..11]
Q1 Q2
Q4 Q3
RCLK[38..43]
R2
CLK[8..11]
R3
RCLK[32..37]
RCLK[12..21] RCLK[22..31]
B1 B2
CLK[4..7]
Note to Figure 5–3:
(1) A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and
another four core signals can drive into RCLK[54..63] at any one time.
Figure 5–4. RCLK Networks (EP4S40G5, EP4S100G3, EP4S100G4, EP4S100G5, EP4SE360, EP4SE530, EP4SE820,
EP4SGX290, EP4SGX360, and EP4SGX530 Devices) ⁽¹⁾, ⁽²⁾, ⁽³⁾
CLK[12..15]
T1 T2
L1
R1
RCLK[82..87] RCLK[54..63] RCLK[44..53] RCLK[76..81]
RCLK[0..5]
CLK[0..3] L2
L3
RCLK[6..11]
Q1 Q2
Q4 Q3
RCLK[38..43]
R2 CLK[8..11]
R3
RCLK[32..37]
RCLK[64..69] RCLK[12..21] RCLK[22..31] RCLK[70..75]
L4
R4
B1 B2
CLK[4..7]
Notes to Figure 5–4:
(1) The corner RCLK[64..87] can only be fed by their respective corner PLL outputs. For more information about connectivity, refer to Table 5–6 on
page 5–13.
(2) The EP4S40G5 and EP4SE360 devices have up to eight PLLs. For more information about PLL availability, refer to Table 5–7 on page 5–19.
(3) A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and
another four core signals can drive into RCLK[54..63] at any one time.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1