EP4SE360F35I4 Datasheet, PDF (279/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–55
Table 7–20. DQS Configuration Block Bit Sequence (Part 2 of 2)
Bit
Bit Name
34..36
37
38
39
40
41
42
43
44
45
octdelaysetting2[0..2]
enadataoutbypass
enadqsenablephasetransferreg
enaoctphasetransferreg
enaoutputphasetransferreg
enainputphasetransferreg
resyncinputphaseinvert
dqsenablectrlphaseinvert
dqoutputphaseinvert
dqsoutputphaseinvert
Document Revision History
Table 7–21 lists the revision history for this chapter.
Table 7–21. Document Revision History (Part 1 of 2)
Date
February 2011
March 2010
Version
Changes
■ Updated Table 7–5, Table 7–6, Table 7–11, Table 7–19, and Table 7–20.
■ Added Table 7–12.
■ Updated Figure 7–36.
3.2
■ Removed Table 7-1 and Table 7-6.
■ Applied new template.
■ Minor text edits.
■ Updated Figure 7–8, Figure 7–11, Figure 7–23, Figure 7–24, Figure 7–29, Figure 7–31,
and Figure 7–36.
■ Added Figure 7–9 and Figure 7–12.
■ Added Table 7–7.
3.1 ^{■ Updated Table 7–1, Table 7–2, Table 7–3, Table 7–4, Table 7–6, Table 7–8 and Table 7–19.}
■ Added note to the “Memory Interfaces Pin Support” section.
■ Changed “DLL1 through DLL4” to “DLL0 through DLL3” throughout.
■ Added frequency mode 7 throughout.
■ Minor text edits.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1