EP4SE360F35I4 Datasheet, PDF (89/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 4: DSP Blocks in Stratix IV Devices
4–9
Stratix IV DSP Block Resource Descriptions
Stratix IV DSP Block Resource Descriptions
The DSP block consists of the following elements:
■ Input register bank
■ Four two-multiplier adders
■ Pipeline register bank
■ Two second-stage adders
■ Four rounding and saturation logic units
■ Second adder register and output register bank
Figure 4–6 shows a detailed overall architecture of the top half of the DSP block.
Table 4–9 on page 4–34 shows a list of DSP block dynamic signals.
Figure 4–6. Half DSP Block Architecture
chainin[ ] (3)
scanina[ ]
clock[3..0]
ena[3..0]
alcr[3..0]
zero_loopback
accum_sload
zero_chainout
chainout_round
chainout_saturate
signa
signb
output_round
output_saturate
rotate
shift_right
overflow (1)
chainout_sat_overflow (2)
dataa_0[ ]
datab_0[ ]
dataa_1[ ]
loopback
datab_1[ ]
dataa_2[ ]
result[ ]
datab_2[ ]
dataa_3[ ]
datab_3[ ]
Half-DSP Block
scanouta
chainout
Notes to Figure 4–6:
(1) Block output for accumulator overflow and saturate overflow.
(2) Block output for saturation overflow of chainout.
(3) The chainin port must only be connected to chainout of the previous DSP blocks and must not be connected to general routings.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1