EP4SE360F35I4 Datasheet, PDF (289/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
8–9
ALTLVDS Port List
ALTLVDS Port List
Table 8–7 lists the interface signals for an LVDS transmitter and receiver.
Table 8–7. Port List of the LVDS Interface (ALTLVDS) ⁽¹⁾, ⁽²⁾ (Part 1 of 3)
Port Name
Input /
Output
Description
PLL Signals
pll_areset
Input
Asynchronous reset to the LVDS transmitter and receiver PLL. The
minimum pulse width requirement for this signal is 10 ns.
LVDS Transmitter Interface Signals
tx_in[ ]
Input
tx_inclock
Input
tx_enable ⁽³⁾
tx_out
tx_outclock
tx_coreclock ⁽³⁾
tx_locked
Input
Output
Output
Output
Output
The data bus width per channel is the same as the serialization factor (SF).
Input data must be synchronous to the tx_coreclock signal.
Reference clock input for the transmitter PLL.
The ALTLVDS MegaWizard Plug-In Manager software automatically selects
the appropriate PLL multiplication factor based on the data rate and
reference clock frequency selection.
For more information about the allowed frequency range for this reference
clock, refer to the “High-Speed I/O Specification” section in the DC and
Switching Characteristics for Stratix IV Devices chapter.
This port is instantiated only when you select the Use External PLL option
in the MegaWizard Plug-In Manager software. This input port must be
driven by the PLL instantiated though the ALTPLL MegaWizard Plug-In
Manager software.
LVDS transmitter serial data output port. tx_out is clocked by a serial clock
generated by the left and right PLL.
The frequency of this clock is programmable to be the same as the data
rate, half the data rate, or one-fourth the data rate. The phase offset of this
clock, with respect to the serial data, is programmable in increments of 45°.
FPGA fabric-transmitter interface clock. The parallel transmitter data
generated in the FPGA fabric must be clocked with this clock.
This port is not available when you select the Use External PLL option in the
MegaWizard Plug-In Manager software. The FPGA fabric-transmitter
interface clock must be driven by the PLL instantiated through the ALTPLL
MegaWizard Plug-In Manager software.
When high, this signal indicates that the transmitter PLL is locked to the
input reference clock.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1