EP4SE360F35I4 Datasheet, PDF (142/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–26
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Any of the output counters (C[9..0] on the top and bottom PLLs and C[6..0] on the
left and right PLLs) or the M counter can feed the dedicated external clock outputs, as
shown in Figure 5–20 and Figure 5–21. Therefore, one counter or frequency can drive
all output pins available from a given PLL.
Each left and right PLL supports two clock I/O pins, configured as either two
single-ended I/Os or one differential I/O pair. When using both pins as single-ended
I/Os, one of them can be the clock output while the other pin is the external feedback
input (FB) pin. Therefore, for single-ended I/O standards, the left and right PLLs only
support external feedback mode.
Figure 5–21. External Clock Outputs for Left and Right PLLs
C0
C1
C2
LEFT/RIGHT
C3
PLLs
C4
C5
C6
m(fbout)
clkena0 (3)
clkena1 (3)
Internal Logic
PLL_<L2, L3, R2, R3>_CLKOUT0n/FB_CLKOUT0p (1), (2)
PLL_<L2, L3, R2, R3>_FB_CLKOUT0p/CLKOUT0n (1), (2)
Notes to Figure 5–21:
(1) You can feed these clock output pins using any one of the C[6..0], m counters.
(2) The CLKOUT0p and CLKOUT0n pins are dual-purpose I/O pins that you can use as two single-ended outputs or one single-ended output and
one external feedback input pin.
(3) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
Each pin of a single-ended output pair can either be in-phase or 180° out-of-phase.
The Quartus II software places the NOT gate in the design into the IOE to implement
the 180° phase with respect to the other pin in the pair. The clock output pin pairs
support the same I/O standards as standard output pins (in the top and bottom
banks) as well as LVDS, LVPECL, differential High-Speed Transceiver Logic (HSTL),
and differential SSTL.
f To determine which I/O standards are supported by the PLL clock input and output
pins, refer to the I/O Features in Stratix IV Devices chapter.
Stratix IV PLLs can also drive out to any regular I/O pin through the GCLK or RCLK
network. You can also use the external clock output pins as user I/O pins if you do
not need external PLL clocking.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation