EP4SE360F35I4 Datasheet, PDF (165/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
5–49
Table 5–11. Top and Bottom PLL Reprogramming Bits (Part 2 of 2)
Block Name
Loop Filter Capacitor ⁽⁴⁾
Loop Filter Resistor
Unused CP/LF
Total number of bits
Number of Bits
Counter
0
0
0
—
Other ⁽¹⁾
2
5
7
—
Total
2
5
7
234
Notes to Table 5–11:
(1) Includes two control bits, rbypass, for bypassing the counter, and rselodd, to select the output clock duty
cycle.
(2) The LSB for the C9 low-count value is the first bit shifted into the scan chain for the top and bottom PLLs.
(3) The LSB for the C6 low-count value is the first bit shifted into the scan chain for the left and right PLLs.
(4) The MSB for the loop filter is the last bit shifted into the scan chain.
Table 5–11 lists the scan chain order of PLL components for the top and bottom PLLs,
which have 10 post-scale counters. The order of bits is the same for the left and right
PLLs, but the reconfiguration bits start with the C6 post-scale counter.
Figure 5–41 shows the scan-chain order of PLL components for the top and bottom
PLLs.
Figure 5–41. Scan-Chain Order of PLL Components for Top and Bottom PLLs ⁽¹⁾
DATAIN
LF K CP
N
MSB
LSB
M
C0
C6
C5
C4
C3
C2
C1
C7
C8
C9
DATAOUT
Note to Figure 5–41:
(1) Left and right PLLs have the same scan-chain order. The post-scale counters end at C6.
Figure 5–42 shows the scan-chain bit-order sequence for post-scale counters in all
Stratix IV PLLs.
Figure 5–42. Scan-Chain Bit-Order Sequence for Post-Scale Counters in Stratix IV PLLs
HB
HB
HB
HB
HB
HB
HB
HB
0
1
2
3
4
5
6
7
rbypass
DATAIN
LB
LB
LB
LB
LB
LB
LB
LB
DATAOUT
0
1
2
3
4
5
rselodd
6
7
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1