EP4SE360F35I4 Datasheet, PDF (368/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

10–32
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Passive Serial Configuration
Table 10–7. PS Timing Parameters for Stratix IV Devices (Part 2 of 2) (Note 1)
Symbol
Parameter
Minimum
Maximum
Units
t_F
t_CD2UM
t_CD2CU
Input fall time
CONF_DONE high to user mode (4)
CONF_DONE high to CLKUSR enabled
—
40
ns
55
150
s
4 × maximum
DCLK period
—
—
t_CD2CU + (8532
t_CD2UMC CONF_DONE high to user mode with CLKUSR option on
CLKUSR
—
—
period)
Notes to Table 10–7:
(1) This information is preliminary.
(2) This value is applicable if you do not delay the configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) This value is applicable if you do not delay the configuration by externally holding nSTATUS low.
(4) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device.
(5) Adding up t_CH and t_CL equals to t_CLK. When t_CH is 3.2 ns (min), t_CL must be 4.8 ns and vice versa.
f Device configuration options and how to create configuration files are described in
the Device Configuration Options and Configuration File Formats chapters in volume 2 of
the Configuration Handbook.
PS Configuration Using a Microprocessor
In this PS configuration scheme, a microprocessor controls the transfer of
configuration data from a storage device, such as flash memory, to the target
Stratix IV device.
For more information about configuration and timing information, refer to “PS
Configuration Using a MAX II Device as an External Host” on page 10–25. This
section is also applicable when using a microprocessor as an external host.
PS Configuration Using a Download Cable
1 In this section, the generic term “download cable” includes the Altera USB-Blaster
universal serial bus (USB) port download cable, MasterBlaster serial/USB
communications cable, ByteBlaster II parallel port download cable, ByteBlasterMV
parallel port download cable, and EthernetBlaster download cable.
In a PS configuration with a download cable, an intelligent host (such as a PC)
transfers data from a storage device to the device using the USB Blaster, MasterBlaster,
ByteBlaster II, EthernetBlaster, or ByteBlasterMV cable.
After power-up, Stratix IV devices go through a POR. The POR delay depends on the
PORSEL pin setting. When PORSEL is driven low, the standard POR time is
100 ms < T_POR < 300 ms. When PORSEL is driven high, the fast POR time is
4 ms < T_POR < 12 ms. During POR, the device resets, holds nSTATUS low, and tri-states
all user I/O pins. After the device successfully exits POR, all user I/O pins continue to
be tri-stated. If nIO_pullup is driven low during power-up and configuration, the user
I/O pins and dual-purpose I/O pins will have weak pull-up resistors, which are on
(after POR) before and during configuration. If nIO_pullup is driven high, the weak
pull-up resistors are disabled.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation