EP4SE360F35I4 Datasheet, PDF (341/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Configuration Features
10–5
Power-On Reset Circuit
The POR circuit keeps the entire system in reset until the power supply voltage levels
have stabilized on power-up. After power-up, the device does not release nSTATUS
until V_CC, V_CCAUX, V_CCPT, V_CCPGM, and V_CCPD are above the device’s POR trip point.
On power down, brown-out occurs if the V_CC, V_CCAUX, V_CCPT, V_CCPGM, or V_CCPD drops
below the threshold voltage.
In Stratix IV devices, a pin-selectable option (PORSEL) is provided that allows you to
select between the standard POR time or fast POR time. When PORSEL is driven low,
the standard POR time is 100 ms < T_POR < 300 ms, which has a lower power-ramp rate.
When PORSEL is driven high, the fast POR time is 4 ms < T_POR < 12 ms.
V_CCPGM Pins
Stratix IV devices have a power supply, V_CCPGM, for all the dedicated configuration
pins and dual function pins. The supported configuration voltage is 1.8, 2.5, and 3.0 V.
Stratix IV devices do not support 1.5 V configuration.
Use the V_CCPGM pin to power all dedicated configuration inputs, dedicated
configuration outputs, dedicated configuration bidirectional pins, and some of the
dual functional pins that you use for configuration. With V_CCPGM, the configuration
input buffers do not have to share power lines with the regular I/O buffer in
Stratix IV devices.
The operating voltage for the configuration input pin is independent of the I/O banks
power supply V_CCIO during configuration. Therefore, Stratix IV devices do not need
configuration voltage constraints on V_CCIO.
V_CCPD Pins
Stratix IV devices have a dedicated programming power supply, V_CCPD, which must
be connected to 3.0 V/2.5 V to power the I/O pre-drivers and JTAG I/O pins (TCK,
TMS, TDI, TDO, and TRST).
1 V_CCPGM and V_CCPD must ramp up from 0 V to the desired voltage level within 100 ms
when PORSEL is low or 4 ms when PORSEL is high. If these supplies are not ramped up
within this specified time, your Stratix IV device will not configure successfully. If
your system cannot ramp up the power supplies within 100 ms or 4 ms, you must
hold nCONFIG low until all the power supplies are stable.
1 V_CCPD must be greater than or equal to V_CCIO of the same bank. If V_CCIO of the bank is
set to 3.0 V, V_CCPD must be powered up to 3.0 V. If the V_CCIO of the bank is powered to
2.5 V or lower, V_CCPD must be powered up to 2.5 V.
For more information about configuration pins power supply, refer to “Device
Configuration Pins” on page 10–39.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1