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EP4SE360F35I4 Datasheet, PDF (276/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced
7–52
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
The output path is designed to route combinatorial or registered SDR outputs and
full-rate or half-rate DDR outputs from the FPGA core. Half-rate data is converted to
full-rate using the HDR block, clocked by the half-rate clock from the PLL. The
resynchronization registers are also clocked by the same 0° system clock, except in the
DDR3 SDRAM interface. In DDR3 SDRAM interfaces, the leveling registers are
clocked by the write-leveling clock.
For more information about the write-leveling delay chain, refer to “Leveling
Circuitry” on page 7–46.
The output-enable path has a structure similar to the output path. You can have a
combinatorial or registered output in SDR applications and you can use half-rate or
full-rate operation in DDR applications. Also, the ouput-enable path’s
resynchronization registers have a structure similar to the output path registers,
ensuring that the output-enable path goes through the same delay and latency as the
output path.
Delay Chain
Stratix IV devices have run-time adjustable delay chains in the I/O blocks and the
DQS logic blocks. You can control the delay chain setting through the I/O or the DQS
configuration block output. Figure 7–33 shows the delay chain ports.
Figure 7–33. Delay Chain
delayctrlin [3..0]
<use finedelayctrlin>
finedelayctrlin
datain
Δt
0
dataout
Δt
1
Every I/O block contains the following:
■ Two delay chains in a series between the output registers and the output buffer
■ One delay chain between the input buffer and the input register
■ Two delay chains between the output enable and the output buffer
■ Two delay chains between the OCT RT enable control register and the output
buffer
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation