EP4SE360F35I4 Datasheet, PDF (152/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–36
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Equation 5–2 shows the coarse-resolution phase shifts are implemented by delaying
the start of the counters for a predetermined number of counter clocks.
Equation 5–2. Coarse-Resolution Phase Shift
Φ_coarse =
C−1
f_Vco
(C − 1)N
=
Mf_REF
where C is the count value set for the counter delay time (this is the initial setting in
the “PLL usage” section of the compilation report in the Quartus II software). If the
initial value is 1, C – 1 = 0° phase shift.
Figure 5–31 shows an example of phase-shift insertion with fine resolution using the
VCO phase-taps method. The eight phases from the VCO are shown and labeled for
reference. For this example, CLK0 is based on the 0phase from the VCO and has the C
value for the counter set to one. The CLK1 signal is divided by four, two VCO clocks
for high time and two VCO clocks for low time. CLK1 is based on the 135° phase tap
from the VCO and also has the C value for the counter set to one. In this case, the two
clocks are offset by 3  _FINE. CLK2 is based on the 0phase from the VCO but has the
C value for the counter set to three. This arrangement creates a delay of 2  _COARSE
(two complete VCO periods).
Figure 5–31. Delay Insertion Using VCO Phase Output and Counter Delay Time
1/8 t_VCO
t_VCO
0
45
90
135
180
225
270
315
CLK0
CLK1
CLK2
t_d0-1
t_d0-2
You can use coarse- and fine-phase shifts to implement clock delays in Stratix IV
devices.
Stratix IV devices support dynamic phase-shifting of VCO phase taps only. You can
reconfigure the phase shift any number of times. Each phase shift takes about one
SCANCLK cycle, allowing you to implement large phase shifts quickly.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation