EP4SE360F35I4 Datasheet, PDF (104/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

4–24
Figure 4–15. Loopback Mode for a Half DSP Block
zero_loopback
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
output_round
output_saturate
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
overflow (1)
dataa_0[17..0]
loopback
datab_0[17..0]
+
dataa_1[17..0]
result[ ]
datab_1[17..0]
Half-DSP Block
Note to Figure 4–15:
(1) Block output for accumulator overflow and saturate overflow.
18 x 18 Complex Multiply
You can configure the DSP block to implement complex multipliers using
two-multiplier adder mode. A single half DSP block can implement one 18-bit
complex multiplier.
Equation 4–4 shows a complex multiplication.
Equation 4–4. Complex Multiplication Equation
(a + jb) × (c + jd) = ((a × c) – (b × d)) + j((a × d) + (b × c))
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation