EP4SE360F35I4 Datasheet, PDF(198/432 Page) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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EP4SE360F35I4 Datasheet, PDF (198/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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6â24

Chapter 6: I/O Features in Stratix IV Devices

On-Chip Termination Support and I/O Termination Schemes

f For more information about pin connection guidelines, refer to the Stratix IV GX and

Stratix IV E Device Family Pin Connection Guidelines.

The Stratix IV VCCPD power pins must be connected to a 2.5- or 3.0-V power supply.

Using these power pins to supply the pre-driver power to the output buffers increases

the performance of the output pins. Table 6â5 lists Stratix IV MultiVolt I/O support.

Table 6â5. Stratix IV MultiVolt I/O Support (1)

Input Signal (V)

Output Signal (V)

VCCIO (V) (3)

1.2 1.5 1.8 2.5 3.0 3.3 1.2 1.5 1.8 2.5 3.0 3.3

1.2

Y

â

Y

â

1.5

â

Y

â

Y

â

1.8

â

Y

â

Y

â

2.5

â

Y

Y (2)

â

Y

â

3.0

â

Y

â

Y

â

Notes to Table 6â5:

(1) The pin current may be slightly higher than the default value. You must verify that the driving deviceâs VOL maximum and VOH minimum voltages

do not violate the applicable Stratix IV VIL maximum and VIH minimum voltage specifications.

(2) Altera recommends that you use an external clamping diode on the I/O pins when the input signal is 3.0 V or 3.3 V. You have the option to use

an internal clamping diode for column I/O pins.

(3) Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one VCCIO, either 1.2, 1.5, 1.8, or 3.0 V. The LVDS I/O standard

is not supported when VCCIO is 3.0 V. The LVDS input operations are supported when VCCIO is 1.2 V, 1.5 V, 1.8 V, or 2.5 V. The LVDS output

operations are only supported when VCCIO is 2.5 V.

On-Chip Termination Support and I/O Termination Schemes

Stratix IV devices feature dynamic series and parallel OCT to provide I/O impedance

matching and termination capabilities. OCT maintains signal quality, saves board

space, and reduces external component costs.

Stratix IV devices support:

â On-chip series termination (RS) with calibration

â On-chip series termination (RS) without calibration

â On-chip Parallel termination (RT) with calibration

â Dynamic series termination for single-ended I/O standards

â Dynamic Parallel termination for single-ended I/O standards

â On-chip differential termination (RD) for differential LVDS I/O standards

Stratix IV devices support OCT in all I/O banks by selecting one of the OCT I/O

standards.

These devices also support OCT RS and RT in the same I/O bank for different I/O

standards if they use the same VCCIO supply voltage. You can independently configure

each I/O in an I/O bank to support OCT RS, programmable current strength, or OCT

RT.

1 You cannot configure both OCT RS and programmable current strength for the same

I/O buffer.

Stratix IV Device Handbook

Volume 1

September 2012 Altera Corporation

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