EP4SE360F35I4 Datasheet, PDF (383/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Device Configuration Pins
10–47
Table 10–12 lists the dedicated JTAG pins. JTAG pins must be kept stable before and
during configuration to prevent accidental loading of JTAG instructions. The TDI,
TMS, and TRST pins have weak internal pull-up resistors, while TCK has a weak
internal pull-down resistor (typically 25 k). If you plan to use the SignalTap^®
embedded logic array analyzer, you must connect the JTAG pins of the Stratix IV
device to a JTAG header on your board.
Table 10–12. Dedicated JTAG Pins
Pin
Name
TDI
TDO
TMS
TCK
TRST
User
Mode
N/A
N/A
N/A
N/A
N/A
Pin Type
Description
Test data
input
Serial input pin for instructions as well as test and programming data. Data is shifted on
the rising edge of TCK. The TDI pin is powered by the 2.5-V/3.0-V V_CCPD supply.
If the JTAG interface is not required on your board, you can disable the JTAG circuitry by
connecting this pin to logic high using a 1-k resistor.
Test data
output
Serial data output pin for instructions as well as test and programming data. Data is
shifted out on the falling edge of TCK. The pin is tri-stated if data is not being shifted out of
the device. The TDO pin is powered by V_CCPD. For recommendations about connecting a
JTAG chain with multiple voltages across the devices in the chain, refer to the JTAG
Boundary Scan Testing in Stratix IV Devices chapter.
If the JTAG interface is not required on your board, you can disable the JTAG circuitry by
leaving this pin unconnected.
Test mode
select
Input pin that provides the control signal to determine the transitions of the TAP controller
state machine. TMS is evaluated on the rising edge of TCK. Therefore, you must set up TMS
before the rising edge of TCK. Transitions within the state machine occur on the falling
edge of TCK after the signal is applied to TMS. The TMS pin is powered by 2.5-V/3.0-V
V_CCPD.
If the JTAG interface is not required on your board, you can disable the JTAG circuitry by
connecting this pin to logic high using a 1-k resistor.
Test clock
input
Clock input to the BST circuitry. Some operations occur at the rising edge, while others
occur at the falling edge. The TCK pin is powered by the 2.5-V/3.0-V V_CCPD supply.
It is expected that the clock input waveform have a nominal 50% duty cycle.
If the JTAG interface is not required on your board, you can disable the JTAG circuitry by
connecting TCK to GND.
Test reset
input
(optional)
Active-low input to asynchronously reset the boundary-scan circuit. The TRST pin is
optional according to IEEE Std. 1149.1. The TRST pin is powered by the 2.5-V/3.0-V V_CCPD
supply.
Hold TMS at 1 or keep TCK static while TRST is changed from 0 to 1.
If the JTAG interface is not required on your board, you can disable the JTAG circuitry by
connecting the TRST pin to GND.
f For more information about the pin connection recommendations, refer to the
Stratix IV GX and Stratix IV E Device Family Pin Connection Guidelines.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1