EP4SE360F35I4 Datasheet, PDF (192/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

6–18
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
■ On-chip series termination without calibration
■ On-chip parallel termination with calibration
■ On-chip differential termination
■ PCI clamping diode
I/O registers are composed of the input path for handling data from the pin to the
core, the output path for handling data from the core to the pin, and the output-enable
(OE) path for handling the OE signal to the output buffer. These registers allow faster
source-synchronous register-to-register transfers and resynchronization. The input
path consists of the DDR input registers, alignment and synchronization registers,
and HDR. You can bypass each block of the input path.
The output and OE paths are divided into output or OE registers, alignment registers,
and HDR blocks. You can bypass each block of the output and OE paths.
Figure 6–17 shows the Stratix IV IOE structure.
Figure 6–17. IOE Structure in Stratix IV Devices ⁽¹⁾, ⁽²⁾, ⁽³⁾, ⁽⁴⁾
Firm Core
DQS Logic Block
OE
from
Core
2
Half Data
Rate Block
Alignment
Registers
OE Register
PRN
DQ
D5_OCT
D6_OCT
Dynamic OCT Control (2)
Write
Data
from
Core
clkout
To
Core
To
Core
4
Half Data
Rate Block
OE Register
PRN
DQ
Alignment
Registers
Output Register
PRN
DQ
Output Register
PRN
DQ
D3_0
Delay
D5, D6
Delay
VCCIO
VCCIO
PCI Clamp
D5, D6
Delay
Programmable
Current
Strength and
Slew Rate
Control
Output Buffer
Programmable
Pull-Up Resistor
From OCT
Calibration
Block
On-Chip
Termination
D2 Delay
Open Drain
Input Buffer
D3_1
Delay
D1
Delay
Input Register
PRN
DQ
Bus-Hold
Circuit
Read
Data
4
to
Core
Half Data
Rate Block
Alignment and
Synchronization
Registers
DQS
CQn
D4 Delay
Input Register
PRN
DQ
Input Register
PRN
DQ
clkin
Notes to Figure 6–17:
(1) The following features are not supported by true differential standards: open drain or tri-state output,; programmable current strength and slew
rate control; PCI Clamp; programmable pull-up resistor; bus-hold circuit.
(2) The D3_0 and D3_1 delays have the same available settings in the Quartus^® II software
(3) One dynamic OCT control is available per DQ/DQS group.
(4) Column I/O supports PCI/PCI-X with an on-chip clamp diode. Row I/O supports PCI/PCI-X with an external clamp diode.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation