EP4SE360F35I4 Datasheet, PDF (304/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–24
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
DPA Mode
Figure 8–19 shows the DPA mode datapath, where all the hardware blocks mentioned
in “Receiver Hardware Blocks” on page 8–19 are active. The DPA block chooses the
best possible clock (DPA_diffioclk) from the eight fast clocks sent by the left and right
PLL. This serial DPA_diffioclk clock is used for writing the serial data into the
synchronizer. A serial LVDS_diffioclk clock is used for reading the serial data from
the synchronizer. The same LVDS_diffioclk clock is used in data realignment and
deserializer blocks.
Figure 8–19. Receiver Datapath in DPA Mode ⁽¹⁾, ⁽²⁾, ⁽³⁾
10
rx_out
IOE Supports SDR, DDR, or Non-Registered Datapath
2
IOE
FPGA
Fabric
rx_divfwdclk
rx_outclock
Deserializer
DOUT DIN
Bit Slip
DOUT DIN
2
(LOAD_EN, diffioclk)
diffioclk
Clock Mux
LVDS Receiver
+
rx_in
Synchronizer
DOUT DIN
DPA Circuitry
Retimed
Data
DIN
DPA Clock
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
3 _{(LVDS_LOAD_EN,}
LVDS_diffioclk,
rx_outclk)
Left/Right PLL
rx_inclock
Notes to Figure 8–19:
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
8 Serial LVDS
Clock Phases
LVDS Clock Domain
DPA Clock Domain
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation