EP4SE360F35I4 Datasheet, PDF (167/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
5–51
Bypassing a PLL
Bypassing a PLL counter results in a multiply (m counter) or a divide (n and C0 to C9
counters) factor of one.
Table 5–15 lists the settings for bypassing the counters in Stratix IV PLLs.
Table 5–15. PLL Counter Settings
PLL Scan Chain Bits [0..8] Settings
LSB
MSB
Description
X X X X X X X X 1 ⁽¹⁾ PLL counter bypassed
X
X
X
X
X
X
X
X
0 ⁽¹⁾
PLL counter not bypassed because
bit 8 (MSB) is set to 0
Note to Table 5–15:
(1) Counter-bypass bit.
1 To bypass any of the PLL counters, set the bypass bit to 1. The values on the other bits
are ignored. To bypass the VCO post-scale counter (K), set the corresponding bit to 0.
Dynamic Phase-Shifting
The dynamic phase-shifting feature allows the output phases of individual PLL
outputs to be dynamically adjusted relative to each other and to the reference clock,
without having to send serial data through the scan chain of the corresponding PLL.
This feature simplifies the interface and allows you to quickly adjust the clock-to-out
(t_CO) delays by changing the output clock phase-shift in real time. This adjustment is
achieved by incrementing or decrementing the VCO phase-tap selection to a given C
counter or to the M counter. The phase is shifted by 1/8 of the VCO frequency at a
time. The output clocks are active during this phase-reconfiguration process.
Table 5–16 lists the control signals that are used for dynamic phase-shifting.
Table 5–16. Dynamic Phase-Shifting Control Signals (Part 1 of 2)
Signal Name
PHASECOUNTERSELECT
[3..0]
PHASEUPDOWN
PHASESTEP
Description
Counter select. Four bits decoded to
select either the M or one of the C
counters for phase adjustment. One
address maps to select all C counters.
This signal is registered in the PLL on
the rising edge of SCANCLK.
Selects dynamic phase shift direction;
1 = UP; 0 = DOWN. Signal is registered
in the PLL on the rising edge of
SCANCLK.
Logic high enables dynamic phase
shifting.
Source
Logic array or I/O pins
Logic array or I/O pin
Logic array or I/O pin
Destination
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1