EP4SE360F35I4 Datasheet, PDF (29/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Table 1–4 lists the Stratix IV E device features.
Table 1–4. Stratix IV E Device Features
Feature
EP4SE230
EP4SE360
EP4SE530
EP4SE820
Package Pin Count
780
780
1152
1152
1517
1760
1152
1517
1760
ALMs
91,200
141,440
212,480
325,220
LEs
228,000
353,600
531,200
813,050
High-Speed LVDS
SERDES (up to
1.6 Gbps) ⁽¹⁾
56
56
88
88
112
112
88
112
132
SPI-4.2 Links
3
3
4
4
6
4
6
6
M9K Blocks
(256 x 36 bits)
1,235
1,248
1,280
1610
M144K Blocks
(2048 x 72 bits)
22
48
64
60
Total Memory
(MLAB+M9K+
M144K) Kb
17,133
22,564
27,376
33,294
Embedded Multipliers
(18 x 18) ⁽²⁾
1,288
1,040
1,024
960
PLLs
User I/Os ⁽³⁾
4
4
8
488
488
744
8
12
12
8
12
12
744
976
976
744 ⁽⁴⁾ 976 ⁽⁴⁾ 1120 ⁽⁴⁾
Speed Grade
(fastest to slowest)
–2, –3, –4 –2, –3, –4 –2, –3, –4 –2, –3, –4 –2, –3, –4 –2, –3, –4 –3, –4 –3, –4 –3, –4
Notes to Table 1–4:
(1) The user I/O count from the pin-out files include all general purpose I/Os, dedicated clock pins, and dual purpose configuration pins. Transceiver pins
and dedicated configuration pins are not included in the pin count.
(2) Four multiplier adder mode.
(3) Total pairs of high-speed LVDS SERDES take the lowest channel count of R_X/T_X.
(4) This data is preliminary.