EP4SE360F35I4 Datasheet, PDF (176/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

6–2
Chapter 6: I/O Features in Stratix IV Devices
I/O Standards Support
■ Programmable delay
■ Programmable bus-hold circuit
■ Programmable pull-up resistor
■ Open-drain output
■ Serial, parallel, and dynamic on-chip termination (OCT)
■ Differential OCT
■ Programmable pre-emphasis
■ Programmable equalization
■ Programmable differential output voltage (V_OD)
This chapter contains the following sections:
■ “I/O Standards Support”
■ “I/O Banks” on page 6–5
■ “I/O Structure” on page 6–17
■ “On-Chip Termination Support and I/O Termination Schemes” on page 6–24
■ “OCT Calibration” on page 6–32
■ “Termination Schemes for I/O Standards” on page 6–38
■ “Design Considerations” on page 6–46
I/O Standards Support
Stratix IV devices support a wide range of industry I/O standards. Table 6–1 lists the
I/O standards Stratix IV devices support, as well as the typical applications. These
devices support V_CCIO voltage levels of 3.0, 2.5, 1.8, 1.5, and 1.2 V.
Table 6–1. I/O Standards and Applications for Stratix IV Devices (Part 1 of 2)
I/O Standard
3.3-V LVTTL/LVCMOS ⁽¹⁾, ⁽²⁾
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.0-V PCI/PCI-X
SSTL-2 Class I and II
SSTL-18 Class I and II
SSTL-15 Class I and II
HSTL-18 Class I and II
HSTL-15 Class I and II
HSTL-12 Class I and II
Differential SSTL-2 Class I and II
Differential SSTL-18 Class I and II
Application
General purpose
General purpose
General purpose
General purpose
General purpose
PC and embedded system
DDR SDRAM
DDR2 SDRAM
DDR3 SDRAM
QDRII/RLDRAM II
QDRII/QDRII+/RLDRAM II
General purpose
DDR SDRAM
DDR2 SDRAM
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation