EP4SE360F35I4 Datasheet, PDF (267/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

DQS Logic Block
Each DQS/CQ and CQn pin is connected to a separate DQS logic block, which consists of the DQS delay chains, update enable
circuitry, and DQS postamble circuitry, as shown in Figure 7–24.
Figure 7–24. Stratix IV DQS Logic Block
DQS Delay Chain
Bypass
DQS/CQ or
CQn Pin
dqsin
1xx
000 dqsbusout
001
010
011
DQS Enable
dqsin
phasectrlin[2:0]
dqsbusout
DQS bus
dqsenable (2)
PRE
QD
6
6
DQS Enable Control
0
0
6
1
6
1
<dqs_ctrl_latches_enable>
Phase ooffffsseettctrlin6[5:0]1
settings from the ₀
DQS phase-shift
6
DQ
6
DQ
dqsupdateen
Update
Enable
Resynchronization
Clock _clk
circuitry
Circuitry
<dqs_offsetctrl_enable>
DQS delay
6
settings from the _{delayctrlin [5:0]}
DQS phase-shift
circuitry
Input Reference
Clock (1)
Postamble
Enable
dqsenablein
delayctrlin
phasectrlin
6
4
phaseinvertctrl
0111
0110
0101
0
0100
0011
1
0010
0001
<level_dqs_enable> ⁰⁰⁰⁰
postamble control clock
0
01
1
0 dqsenableout
1
enaphasetransferreg
<delay_dqs_enable_by_half_cycle>
Notes to Figure 7–24:
(1) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For more information, refer to Table 7–5 on page 7–33 through Table 7–17 on page 7–39.
(2) The dqsenable signal can also come from the Stratix IV FPGA fabric.