EP4SE360F35I4 Datasheet, PDF (299/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
8–19
Figure 8–13 shows device on-chip termination.
Figure 8–13. On-Chip Differential I/O Termination
LVDS
Transmitter
Z₀ = 50 Ω
Stratix IV Differential
Receiver with On-Chip
100 Ω Termination
R_D
Z₀ = 50 Ω
Receiver Hardware Blocks
The differential receiver has the following hardware blocks:
■ “DPA Block” on page 8–19
■ “Synchronizer” on page 8–20
■ “Data Realignment Block (Bit Slip)” on page 8–20
■ “Deserializer” on page 8–22
DPA Block
The DPA block takes in high-speed serial data from the differential input buffer and
selects one of the eight phases generated by the left and right PLL to sample the data.
The DPA chooses a phase closest to the phase of the serial data. The maximum phase
offset between the received data and the selected phase is 1/8 UI, which is the
maximum quantization error of the DPA. The eight phases of the clock are equally
divided, offering a 45^° resolution.
Figure 8–14 shows the possible phase relationships between the DPA clocks and the
incoming serial data.
Figure 8–14. DPA Clock Phase to Serial Data Timing Relationship ⁽¹⁾
rx_in
D0
D1
D2
D3
D4
Dn
0˚
45˚
90˚
135˚
180˚
225˚
270˚
315˚
0.125T_vco
T_vco
Note to Figure 8–14:
(1) T_VCO is defined as the PLL serial clock period.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1