EP4SE360F35I4 Datasheet, PDF (90/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

4–10
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV DSP Block Resource Descriptions
Input Registers
All of the DSP block registers are triggered by the positive edge of the clock signal and
are cleared after power up. Each multiplier operand can feed an input register or go
directly to the multiplier, bypassing the input registers. The following DSP block
signals control the input registers within the DSP block:
■ clock[3..0]
■ ena[3..0]
■ aclr[3..0]
Every DSP block has nine 18-bit data input register banks per half DSP block. Every
half DSP block has the option to use the eight data register banks as inputs to the four
multipliers. The special ninth register bank is a delay register required by modes that
use both the cascade and chainout features of the DSP block. Use the ninth register
bank to balance the latency requirements when using the chained cascade feature.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation