EP4SE360F35I4 Datasheet, PDF (226/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

7–2
Chapter 7: External Memory Interfaces in Stratix IV Devices
Figure 7–1 shows an overview of the memory interface data path that uses all the
Stratix IV I/O element (IOE) features.
Figure 7–1. External Memory Interface Data Path Overview ⁽¹⁾, ⁽²⁾
DLL
Stratix IV FPGA
DQS Logic
Block
Memory
DQS (Read) (3)
DPRAM
(2)
Postamble Enable
Postamble Clock
Postamble
Control
Circuit
DQS Enable
Circuit
4n
2n
2n
Half Data Rate
Input Registers
Alignment &
Synchronization
Registers
DDR Input
Registers
4n
2n
Half Data Rate
Output Registers
Resynchronization Clock
2n
Alignment
Registers
DDR Output
and Output
Enable
Registers
n
DQ (Read) (3)
n
DQ (Write) (3)
Half-Rate
Resynchronization
Clock
Clock Management & Reset ^{DQ Write Clock}
Half-Rate Clock
Alignment Clock
DQS Write Clock
4
2
Half Data Rate
Output Registers
2
Alignment
Registers
DDR Output
and Output
Enable
Registers
DQS (Write) (3)
Notes to Figure 7–1:
(1) You can bypass each register block.
(2) The blocks used for each memory interface may differ slightly. The shaded blocks are part of the Stratix IV IOE.
(3) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read
and write operations.
Memory interfaces use Stratix IV device features such as delay-locked loops (DLLs),
dynamic OCT control, read- and write-leveling circuitry, and I/O features such as
OCT, programmable input delay chains, programmable output delay, slew rate
adjustment, and programmable drive strength.
f For more information about I/O features, refer to the I/O Features in Stratix IV Devices
chapter.
The ALTMEMPHY megafunction instantiates a phase-locked loop (PLL) and PLL
reconfiguration logic to adjust the phase shift based on VT variation. vs
f
For more information about the Stratix IV PLL, refer to the Clock Networks and PLLs in
Stratix IV Devices chapter. For more information about the ALTMEMPHY
megafunction, refer to the External Memory PHY Interface (ALTMEMPHY) (nonAFI)
Megafunction User Guide.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation