EP4SE360F35I4 Datasheet, PDF (284/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–4
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Channels
Figure 8–3 shows a high-level chip overview of the Stratix IV GT and GX devices.
Figure 8–3. High-Speed Differential I/Os with DPA Locations in Stratix IV GT and GX Devices
General Purpose
I/O and Memory
Interface
PLL
PLL PLL
General Purpose
I/O and Memory
Interface
PLL
FPGA Fabric
PLL
(Logic Elements, DSP,
PLL
PLL
Embedded Memory,
PLL
Clock Networks)
PLL
General Purpose
I/O and Memory
Interface
PLL PLL
PLL
General Purpose
I/O and Memory
Interface
LVDS Channels
The Stratix IV device family supports LVDS on both row and column I/O banks. Row
I/Os support true LVDS input with 100- differential input termination (OCT R_D),
and true LVDS output buffers. Column I/Os supports true LVDS input buffers
without OCT R_D. Alternately, you can configure the row and column LVDS pins as
emulated LVDS output buffers that use two single-ended output buffers with an
external resistor network to support LVDS, mini-LVDS, and RSDS standards.
Stratix IV devices offer single-ended I/O refclk support for the LVDS.
Dedicated SERDES and DPA circuitries are implemented on the row I/O banks to
further enhance LVDS interface performance in the device. For column I/O banks,
SERDES is implemented in the core logic because there is no dedicated SERDES
circuitry on column I/O banks.
1 Emulated differential output buffers support tri-state capability starting with the
Quartus II software version 9.1.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation