EP4SE360F35I4 Datasheet, PDF (410/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

11–4
Chapter 11: SEU Mitigation in Stratix IV Devices
User Mode Error Detection
A JTAG instruction, EDERROR_INJECT, is provided to test the capability of the error
detection block. This instruction is able to change the content of the 21-bit JTAG fault
injection register that is used for error injection in Stratix IV devices, enabling the
testing of the error detection block.
1 You can only execute the EDERROR_INJECT JTAG instruction when the device is in user
mode.
Table 11–1 lists the description of the EDERROR_INJECT JTAG instruction.
Table 11–1. EDERROR_INJECT JTAG Instruction
JTAG Instruction
Instruction Code
EDERROR_INJECT
00 0001 0101
Description
This instruction controls the 21-bit JTAG fault
injection register, which is used for error
injection.
You can create a Jam™ file (.jam) to automate the testing and verification process.
This allows you to verify the CRC functionality in-system, on-the-fly, without having
to reconfigure the device. You can then switch to the CRC circuit to check for real
errors induced by an SEU.
You can introduce a single-error or double-errors adjacent to each other to the
configuration memory. This provides an extra way to facilitate design verification and
system fault tolerance characterization. Use the JTAG fault injection register with the
EDERROR_INJECT instruction to flip the readback bits. The Stratix IV device is then
forced into error test mode.
The content of the JTAG fault injection register is not loaded into the fault injection
register during the processing of the last and first frame. It is only loaded at the end of
this period.
1 You can only introduce error injection in the first data frame, but you can monitor the
error information at any time. For more information about the JTAG fault injection
register and fault injection register, refer to “Error Detection Registers” on page 11–7.
Table 11–2 lists how the fault injection register is implemented and describes error
injection.
Table 11–2. Fault Injection Register
Bit
Bit[20..19]
Bit[18..8]
Bit[7..0]
Description
Error Type
Byte Location of
the Injected Error
Error Byte Value
Content
Error Type ⁽¹⁾
Bit[20] Bit[19]
0
1
1
0
0
0
Error injection type
Single-byte error injection
Double-adjacent byte error injection
No error injection
Depicts the location
of the injected error
in the first data
frame.
Depicts the location
of the bit error and
corresponds to the
error injection type
selection.
Note to Table 11–2:
(1) Bit[20] and Bit[19] cannot both be set to 1 as this is not a valid selection. The error detection circuitry decodes this as no error injection.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation