EP4SE360F35I4 Datasheet, PDF (308/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–28
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Interface with the Use External PLL Option Enabled
Example 8–1 shows how to generate three output clocks using an ALTPLL
megafunction.
Example 8–1. Generating Three Output Clocks Using an ALTPLL Megafunction
LVDS data rate = 1 Gbps; serialization factor = 10; input reference clock = 100 MHz
The following settings are used when generating the three output clocks using an ALTPLL megafunction.
The serial clock must be 1000 MHz and the parallel clock must be 100 MHz (serial clock divided by the
serialization factor):
■ c0
■ Frequency = 1000 MHz (multiplication factor = 10 and division factor = 1)
■ Phase shift = –180° with respect to the voltage-controlled oscillator (VCO) clock
■ Duty cycle = 50%
■ c1
■ Frequency = (1000/10) = 100 MHz (multiplication factor = 1 and division factor = 1)
■ Phase shift = (10 - 2) × 360/10 = 288° [(deserialization factor - 2)/deserialization factor] × 360°
■ Duty cycle = (100/10) = 10% (100 divided by the serialization factor)
■ c2
■ Frequency = (1000/10) = 100 MHz (multiplication factor = 1 and division factor = 1)
■ Phase shift = (–180/10) = –18° (c0 phase shift divided by the serialization factor)
■ Duty cycle = 50%
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation