EP4SE360F35I4 Datasheet, PDF (426/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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Chapter 13: Power Management in Stratix IV Devices
Stratix IV Power Technology
Power consumption also affects thermal management. Stratix IV devices offer a TSD
feature that self-monitors the device junction temperature and can be used with
external circuitry for other activities, such as controlling air flow to the Stratix IV
FPGA.
This chapter contains the following sections:
■ “Stratix IV Power Technology”
■ “Stratix IV External Power Supply Requirements”
■ “Temperature Sensing Diode”
Stratix IV Power Technology
The following sections describe Stratix IV programmable power technology.
Programmable Power Technology
Stratix IV devices offer the ability to configure portions of the core, called tiles, for
high-speed or low-power mode of operation performed by the Quartus II software
without user intervention. Setting a tile to high-speed or low-power mode is
accomplished with on-chip circuitry and does not require extra power supplies
brought into the Stratix IV device. In a design compilation, the Quartus II software
determines whether a tile must be in high-speed or low-power mode based on the
timing constraints of the design.
f For more information about how the Quartus II software uses programmable power
technology when compiling a design, refer to AN 514: Power Optimization in Stratix IV
FPGAs.
A Stratix IV tile can consist of the following:
■ Memory logic array block (MLAB)/logic array block (LAB) pairs with routing to
the pair
■ MLAB/LAB pairs with routing to the pair and to adjacent digital signal processing
(DSP)/memory block routing
■ TriMatrix memory blocks
■ DSP blocks
All blocks and routing associated with the tile share the same setting of either
high-speed or low-power mode. By default, tiles that include DSP blocks or memory
blocks are set to high-speed mode for optimum performance. Unused DSP blocks and
memory blocks are set to low-power mode to minimize static power. Clock networks
do not support programmable power technology.
With programmable power technology, faster speed grade FPGAs may require less
power because there are fewer high-speed MLAB and LAB pairs, when compared
with slower speed grade FPGAs. The slower speed grade device may have to use
more high-speed MLAB and LAB pairs to meet performance requirements, while the
faster speed grade device can meet performance requirements with MLAB and LAB
pairs in low-power mode.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation