EP4SE360F35I4 Datasheet, PDF (117/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

September 2012
SIV51005-3.4
SIV51005-3.4
5. Clock Networks and PLLs in Stratix IV
Devices
This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)
which have advanced features in Stratix^® IV devices. It includes details about the
ability to reconfigure the PLL counter clock frequency and phase shift in real time,
allowing you to sweep PLL output frequencies and dynamically adjust the output
clock phase shift.
The Quartus^® II software enables the PLLs and their features without external
devices. The following sections describe the Stratix IV clock networks and PLLs in
detail:
■ “Clock Networks in Stratix IV Devices” on page 5–1
■ “PLLs in Stratix IV Devices” on page 5–19
Clock Networks in Stratix IV Devices
The global clock networks (GCLKs), regional clock networks (RCLKs), and periphery
clock networks (PCLKs) available in Stratix IV devices are organized into hierarchical
clock structures that provide up to 236 unique clock domains (16 GCLKs + 88 RCLKs
+ 132 PCLKs) within the Stratix IV device and allow up to 71 unique GCLK, RCLK,
and PCLK clock sources (16 GCLKs + 22 RCLKs + 33 PCLKs) per device quadrant.
Table 5–1 lists the clock resources available in Stratix IV devices.
Table 5–1. Clock Resources in Stratix IV Devices (Part 1 of 2)
Clock Resource
Clock input pins
GCLK networks
RCLK networks
PCLK networks
GCLKs/RCLKs per
quadrant
Number of Resources Available
Source of Clock Resource
32 Single-ended
(16 Differential)
CLK[0..15]p and CLK[0..15]n pins
16
CLK[0..15]p and CLK[0..15]n pins, PLL clock outputs, and
logic array
64/88 ⁽¹⁾
CLK[0..15]p and CLK[0..15]n pins, PLL clock outputs, and
logic array
56/88/112/132 (33 per device DPA clock outputs, PLD-transceiver interface clocks, horizontal
quadrant) ⁽²⁾
I/O pins, and logic array
32/38 ⁽³⁾
16 GCLKs + 16 RCLKs
16 GCLKs + 22 RCLKs
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Stratix IV Device Handbook
Volume 1
September 2012
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