EP4SE360F35I4 Datasheet, PDF (149/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
5–33
Figure 5–28 shows an example waveform of the phase relationship between the PLL
clocks in external feedback mode.
Figure 5–28. Phase Relationship Between the PLL Clocks in External Feedback Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at
the Register
Clock Port (1)
Dedicated PLL
Clock Outputs (1)
fbin Clock Input Pin
Note to Figure 5–28:
(1) The PLL clock outputs can lead or lag the fbin clock input.
Figure 5–29 shows external feedback mode implementation in Stratix IV devices.
Figure 5–29. External Feedback Mode in Stratix IV Devices
inclk
÷n
PFD CP/LF VCO
÷C0
÷C1
PLL_<#>_CLKOUT#
PLL_<#>_CLKOUT#
fbout
÷m
fbin
external
board
trace
Clock Multiplication and Division
Each Stratix IV PLL provides clock synthesis for PLL output ports using
M/(N* post-scale counter) scaling factors. The input clock is divided by a pre-scale
factor, n, and is then multiplied by the m feedback factor. The control loop drives the
VCO to match f_in (M/N). Each output port has a unique post-scale counter that
divides down the high-frequency VCO. For multiple PLL outputs with different
frequencies, the VCO is set to the least common multiple of the output frequencies
that meets its frequency specifications. For example, if the output frequencies required
from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz within the VCO range). Then the
post-scale counters scale down the VCO frequency for each output port.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1