EP4SE360F35I4 Datasheet, PDF (291/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Transmitter
8–11
Table 8–7. Port List of the LVDS Interface (ALTLVDS) ⁽¹⁾, ⁽²⁾ (Part 3 of 3)
Port Name
dpa_pll_cal_busy
Input /
Output
Output
Description
Busy signal that is asserted high when the PLL calibration occurs.
Reset Signals
rx_reset
rx_fifo_reset
rx_cda_reset
Input
Input
Input
Asynchronous reset to the DPA circuitry and FIFO. The minimum pulse
width requirement for this reset is one parallel clock cycle. This signal
resets DPA and FIFO blocks.
Asynchronous reset to the FIFO between the DPA and the data realignment
circuits. The synchronizer block must be reset after a DPA loses lock
condition and the data checker shows corrupted received data. The
minimum pulse width requirement for this reset is one parallel clock cycle.
This signal resets the FIFO block.
Asynchronous reset to the data realignment circuitry. The minimum pulse
width requirement for this reset is one parallel clock cycle. This signal
resets the data realignment block.
Notes to Table 8–7:
(1) Unless stated, signals are valid in all three modes (non-DPA, DPA, and soft-CDR) for a single channel.
(2) All reset and control signals are active high.
(3) For more information, refer to “LVDS Interface with the Use External PLL Option Enabled” on page 8–26.
f For more information about the LVDS transmitter and receiver settings using
ALTLVDS_TX and ALTLVDS_RX megafunction, refer to the ALTLVDS Megafunction
User Guide.
Differential Transmitter
The Stratix IV transmitter has a dedicated circuitry to provide support for LVDS
signaling. The dedicated circuitry consists of a differential buffer, a serializer, and left
and right PLLs that can be shared between the transmitter and receiver. The
differential buffer can drive out LVDS, mini-LVDS, and RSDS signaling levels. The
serializer takes up to 10 bits wide parallel data from the FPGA fabric, clocks it into the
load registers, and serializes it using shift registers clocked by the left and right PLL
before sending the data to the differential buffer. The MSB of the parallel data is
transmitted first.
1 When using emulated LVDS I/O standards at the differential transmitter, the SERDES
circuitry must be implemented in logic cells but not hard SERDES.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1