EP4SE360F35I4 Datasheet, PDF (309/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Left and Right PLLs (PLL_Lx and PLL_Rx)
8–29
The Equation 8–1 calculations for phase shift assume that the input clock and serial
data are edge aligned. Introducing a phase shift of –180° to sampling clock (c0)
ensures that the input data is center-aligned with respect to the c0, as shown in
Figure 8–22.
Figure 8–22. Phase Relationship for External PLL Interface Signals
inclk0
VCO clk
(internal PLL clk)
c0 (-180
phase shift)
c1 (288
phase shift)
c2 (-18
phase shift)
Serial data
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
Left and Right PLLs (PLL_Lx and PLL_Rx)
The Stratix IV device family contains up to eight left and right PLLs with up to four
PLLs located on the left side and four on the right side of the device. The left PLLs can
support high-speed differential I/O banks on the left side; the right PLLs can support
high-speed differential I/O banks on the right side of the device. The high-speed
differential I/O receiver and transmitter channels use these left and right PLLs to
generate the parallel clocks (rx_outclock and tx_outclock) and high-speed clocks
(diffioclk).
Figure 8–2 on page 8–3 and Figure 8–3 on page 8–4 show the locations of the left and
right PLLs for Stratix IV E, GT, and GX devices. The PLL VCO operates at the clock
frequency of the data rate. Clock switchover and dynamic reconfiguration are allowed
using the left and right PLL in high-speed differential I/O support mode.
f For more information, refer to the Clock Networks and PLLs in Stratix IV Devices
chapter.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1