EP4SE360F35I4 Datasheet, PDF (314/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

8–34
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
Figure 8–27 shows the relationship between the RSKM, TCCS, and the receiver’s SW.
You must calculate the RSKM value to decide whether or not data can be sampled
properly by the LVDS receiver with the given data rate and device. A positive RSKM
value indicates that the LVDS receiver can sample the data properly, whereas a
negative RSKM indicates that it cannot.
Figure 8–27. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode
Timing Diagram
External
Input Clock
Internal
Clock
Time Unit Interval (TUI)
Receiver
Input Data
TCCS
RSKM
SW
TCCS
RSKM
Timing Budget
External
Clock
Internal
Clock
Synchronization
Transmitter
Output Data
TCCS
Receiver
Input Data
Internal
Clock
Falling Edge
TUI
Clock Placement
RSKM
RSKM
SW
TCCS
2
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation