EP4SE360F35I4 Datasheet, PDF (414/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

11–8
Chapter 11: SEU Mitigation in Stratix IV Devices
Error Detection Timing
Table 11–4. Error Detection Registers (Part 2 of 2)
Register
Description
JTAG Update Register
This register is automatically updated with the contents of the error message register one cycle
after the 46-bit register content is validated. It includes a clock enable that must be asserted prior
to being sampled into the JTAG shift register. This requirement ensures that the JTAG update
register is not being written into by the contents of the error message register at the same time
that the JTAG shift register is reading its contents.
User Update Register
This register is automatically updated with the contents of the Error Message Register, one cycle
after the 46-bit register content is validated. It includes a clock enable that must be asserted prior
to being sampled into the User Shift Register. This requirement ensures that the User Update
Register is not being written into by the contents of the Error Message Register at exactly the
same time that the User Shift Register is reading its contents.
JTAG Shift Register
This register is accessible by the JTAG interface and allows the contents of the JTAG Update
Register to be sampled and read by the JTAG instruction SHIFT_EDERROR_REG.
User Shift Register
This register is accessible by the core logic and allows the contents of the User Update Register to
be sampled and read by user logic.
JTAG Fault Injection
Register
This 21-bit register is fully controlled by the JTAG instruction EDERROR_INJECT. This register
holds the information of the error injection that you want in the bitstream.
Fault Injection Register
The content of the JTAG Fault Injection Register is loaded into this 21-bit register when it is being
updated.
Error Detection Timing
When you enable the CRC feature through the Quartus II software, the device
automatically activates the CRC process after entering user mode, after configuration,
and after initialization is complete.
If an error is detected within a frame, CRC_ERROR is driven high at the end of the error
location search, after the error message register is updated. At the end of this cycle,
the CRC_ERROR pin is pulled low for a minimum of 32 clock cycles. If the next frame
contains an error, CRC_ERROR is driven high again after the error message register is
overwritten by the new value. You can start to unload the error message on each
rising edge of the CRC_ERROR pin. Error detection runs until the device is reset.
The error detection circuitry runs off an internal configuration oscillator with a divisor
that sets the maximum frequency. Table 11–5 lists the minimum and maximum error
detection frequencies based on the best performance of the internal configuration
oscillator.
Table 11–5. Minimum and Maximum Error Detection Frequencies
Device Type
Stratix IV
Error Detection
Frequency
100 MHz / 2ⁿ
Maximum Error
Detection Frequency
50 MHz
Minimum Error Detection
Frequency
390 kHz
Valid Divisors (n)
1, 2, 3, 4, 5, 6, 7, 8
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation