EP4SE360F35I4 Datasheet, PDF (65/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
3–9
Memory Modes
Figure 3–6 shows a diagram of the ECC block of the M144K block.
Figure 3–6. ECC Block Diagram of the M144K Block
8
64
Data Input
64
SECDED ⁸
Encoder
64
72
RAM
72
64
SECDED
Array
Encoder
Comparator
8
8
64
Error
Locator
64
Error
Correction
Block
64
Data Output
8
Flag
Generator
3
Status Flags
Memory Modes
Stratix IV TriMatrix memory blocks allow you to implement fully synchronous SRAM
memory in multiple modes of operation. M9K and M144K blocks do not support
asynchronous memory (unregistered inputs). MLABs support asynchronous
(flow-through) read operations.
Depending on which TriMatrix memory block you target, you can use the following:
■ “Single-Port RAM Mode” on page 3–10
■ “Simple Dual-Port Mode” on page 3–11
■ “True Dual-Port Mode” on page 3–14
■ “Shift-Register Mode” on page 3–16
■ “ROM Mode” on page 3–17
■ “FIFO Mode” on page 3–17
c When using the memory blocks in ROM, single-port, simple dual-port, or true
dual-port mode, you can corrupt the memory contents if you violate the setup or
hold-time on any of the memory block input registers. This applies to both read and
write operations.
December 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1