EP4SE360F35I4 Datasheet, PDF (273/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–49
I/O Element Registers
The IOE registers are expanded to allow source-synchronous systems to have faster
register-to-register transfers and resynchronization. Both top and bottom and left and
right IOEs have the same capability. Left and right IOEs have extra features to support
LVDS data transfer.
Figure 7–31 shows the registers available in the Stratix IV input path. The input path
consists of the DDR input registers, resynchronization registers, and HDR block. You
can bypass each block of the input path.
Figure 7–31. Stratix IV IOE Input Registers ⁽¹⁾
DQS/CQ (3), (9)
DQSn (9)
CQn (4)
DQ
Double Data Rate Input Registers
DQ
Differential
Input
Buffer
DFF
Input Reg AI
neg_reg_out
DQ
DQ
DFF
DFF
Input Reg BI Input Reg CI
Alignment & Synchronization Registers
0
0
1
D
Q
datain [0]
D
Q
1
0
1
DQ
DFF
DFF
DQ
DFF
DFF
enaphasetransferreg
enainputcycledelay
<bypass_output_register>(10)
Resynchronization Clock
(resync_clk_2x) (5)
datain [1]
D
Q
DFF
0
D
Q₁
DFF
0
D Q¹
DFF
(2)
DQ
DFF
dataout
dataout
Half Data Rate Registers
directin
D
Q
0
To Core
1
dataout[2]
(7)
DFF
D
Q
To Core
dataout [0]
(7)
DQ
dataoutbypass
(8)
DFF
DQ
DFF
D
Q
DFF
0
1 To Core
dataout [3]
To Core
(7)
dataout [1]
(7)
DQ
DFF
DFF
I/O Clock
Divider (6)
Half-Rate Resynchronization Clock (resync_clk_1x)
to core (7)
Notes to Figure 7–31:
(1) You can bypass each register block in this path.
(2) This is the 0-phase resynchronization clock (from the read-leveling delay chain).
(3) The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a global clock line.
(4) This input clock comes from the CQn logic block.
(5) This resynchronization clock comes from a PLL through the clock network (resync_ck_2x).
(6) The I/O clock divider resides adjacent to the DQS logic block. In addition to the PLL and read-leveled resync clock, the I/O clock divider can also
be fed by the DQS bus or CQn bus.
(7) The half-rate data and clock signals feed into a dual-port RAM in the FPGA core.
(8) You can dynamically change the dataoutbypass signal after configuration to select either the directin input or the output from the half data
rate register to feed dataout.
(9) The DQS and DQSn signals must be inverted for DDR, DDR2, and DDR3 interfaces. When using Altera’s memory interface IPs, the DQS and DQSn
signals are automatically inverted.
(10) The bypass_output_register option allows you to select either the output from the second mux or the output of the fourth alignment/
synchronization register to feed dataout.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1