EP4SE360F35I4 Datasheet, PDF (120/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–4
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
Regional Clock Networks
RCLK networks only pertain to the quadrant they drive into. RCLK networks provide
the lowest clock delay and skew for logic contained within a single device quadrant.
The Stratix IV device IOEs and internal logic within a given quadrant can also drive
RCLKs to create internally generated regional clocks and other high fan-out control
signals; for example, synchronous or asynchronous clears and clock enables.
Figure 5–2 through Figure 5–4 on page 5–5 show the CLK pins and PLLs that can
drive the RCLK networks in Stratix IV devices.
Figure 5–2. RCLK Networks (EP4SE230, EP4SGX70, and EP4SGX110 Devices) ⁽¹⁾
CLK[12..15]
T1
RCLK[54..63] RCLK[44..53]
RCLK[0..5]
CLK[0..3] L2
RCLK[6..11]
Q1 Q2
Q4 Q3
RCLK[38..43]
R2 CLK[8..11]
RCLK[32..37]
RCLK[12..21] RCLK[22..31]
B1
CLK[4..7]
Note to Figure 5–2:
(1) A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and
another four core signals can drive into RCLK[54..63] at any one time.
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation