EP4SE360F35I4 Datasheet, PDF(254/432 Page) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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EP4SE360F35I4 Datasheet, PDF (254/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

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7â30

Chapter 7: External Memory Interfaces in Stratix IV Devices

Stratix IV External Memory Interface Features

Figure 7â21 shows how the DQS phase-shift circuitry is connected to the DQS/CQ

and CQn pins in the device where memory interfaces are supported on all sides of the

Stratix IV device.

Figure 7â21. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry (1), (2)

DLL

Reference

Clock

DQS/CQ

CQn

Ît

DQS/CQ

DQS Logic

Blocks

Ît

CQn

Ît

DLL

Reference

Clock

DQS

Phase-Shift

Circuitry

to IOE

DQS/CQ

CQn

Ît

to

IOE

Ît

to

IOE

to IOE

DQS

Phase-Shift

Circuitry

to

IOE

DQS Logic

Blocks

Ît

CQn

to

IOE

Ît

DQS/CQ

CQn

Ît

to

IOE

Ît

to

IOE

to

IOE

Ît

CQn

to

IOE

Ît

DQS/CQ

DQS

Phase-Shift

Circuitry

to IOE

DQS

Phase-Shift

Circuitry

Ît

DLL

Reference

Clock

CQn

DQS/CQ

CQn

DQS/CQ

DLL

Reference

Clock

Notes to Figure 7â21:

(1) For possible reference input clock pins for each DLL, refer to âDLLâ on page 7â31.

(2) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.

DQS phase-shift circuitry is connected to the DQS logic blocks that control each

DQS/CQ or CQn pin. The DQS logic blocks allow the DQS delay settings to be

updated concurrently at every DQS/CQ or CQn pin.

Stratix IV Device Handbook

Volume 1

February 2011 Altera Corporation

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