EP4SE360F35I4 Datasheet, PDF (255/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–31
DLL
DQS phase-shift circuitry uses a DLL to dynamically control the clock delay needed
by the DQS/CQ and CQn pin. The DLL, in turn, uses a frequency reference to
dynamically generate control signals for the delay chains in each of the DQS/CQ and
CQn pins, allowing it to compensate for PVT variations. The DQS delay settings are
Gray-coded to reduce jitter when the DLL updates the settings. The phase-shift
circuitry needs 1,280 clock cycles to lock and calculate the correct input clock period
when the DLL is in low jitter mode. Otherwise, only 256 clock cycles are needed. Do
not send data during these clock cycles because there is no guarantee that it will be
captured properly. As the settings from the DLL may not be stable until this lock
period has elapsed, be aware that anything using these settings (including the
leveling delay system) may be unstable during this period.
1 You can still use the DQS phase-shift circuitry for any memory interfaces that are less
than 100 MHz. However, the DQS signal may not shift over 2.5 ns. Even if the DQS
signal is not shifted exactly to the middle of the DQ valid window, the I/O element
should still be able to capture the data in low-frequency applications in which a large
amount of timing margin is available.
There are a maximum of four DLLs in a Stratix IV device, located in each corner of the
device. These four DLLs support a maximum of four unique frequencies, with each
DLL running at one frequency. Each DLL can have two outputs with different phase
offsets, which allows one Stratix IV device to have eight different DLL phase shift
settings.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1