EP4SE360F35I4 Datasheet, PDF (37/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

February 2011
SIV51002-3.1
SIV51002-3.1
2. Logic Array Blocks and Adaptive Logic
Modules in Stratix IV Devices
This chapter describes the features of the logic array blocks (LABs) in the Stratix^® IV
core fabric. LABs are made up of adaptive logic modules (ALMs) that you can
configure to implement logic functions, arithmetic functions, and register functions.
LABs and ALMs are the basic building blocks of the Stratix IV device. Use these to
configure logic, arithmetic, and register functions. The ALM provides advanced
features with efficient logic usage and is completely backward-compatible.
This chapter contains the following sections:
■ “Logic Array Blocks”
■ “Adaptive Logic Modules” on page 2–5
Logic Array Blocks
Each LAB consists of ten ALMs, various carry chains, shared arithmetic chains, LAB
control signals, local interconnect, and register chain connection lines. The local
interconnect transfers signals between ALMs in the same LAB. The direct link
interconnect allows the LAB to drive into the local interconnect of its left and right
neighbors. Register chain connections transfer the output of the ALM register to the
adjacent ALM register in the LAB. The Quartus^® II Compiler places associated logic in
the LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and
register chain connections for performance and area efficiency.
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semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
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described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
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Stratix IV Device Handbook
Volume 1
February 2011
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