EP4SE360F35I4 Datasheet, PDF (41/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
2–5
Adaptive Logic Modules
The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control
signals. The MultiTrack interconnect’s inherent low skew allows clock and control
signal distribution in addition to data.
Figure 2–4. LAB-Wide Control Signals
6
Dedicated Row LAB Clocks
6
There are two unique
clock signals per LAB.
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
labclk1
labclk2
syncload
labclkena0
or asyncload
or labpreset
labclkena1
labclkena2
labclr0
labclr1
synclr
Adaptive Logic Modules
The ALM is the basic building block of logic in the Stratix IV architecture. It provides
advanced features with efficient logic usage. Each ALM contains a variety of
LUT-based resources that can be divided between two combinational adaptive LUTs
(ALUTs) and two registers. With up to eight inputs for the two combinational ALUTs,
one ALM can implement various combinations of two functions. This adaptability
allows an ALM to be completely backward-compatible with four-input LUT
architectures. One ALM can also implement any function with up to six inputs and
certain seven-input functions.
February 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1