EP4SE360F35I4 Datasheet, PDF (193/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
6–19
f For more information about I/O registers and how they are used for memory
applications, refer to the External Memory Interfaces in Stratix IV Devices chapter.
3.3-V I/O Interface
Stratix IV I/O buffers support 3.3-V I/O standards. You can use them as transmitters
or receivers in your system. The output high voltage (V_OH), output low voltage (V_OL),
input high voltage (V_IH), and input low voltage (V_IL) levels meet the 3.3-V I/O
standards specifications defined by EIA/JEDEC Standard JESD8-B with margin when
the Stratix IV V_CCIO voltage is powered by 3.0 V.
To ensure device reliability and proper operation, when interfacing with a 3.3-V I/O
system using Stratix IV devices, ensure that you do not violate the absolute maximum
ratings of the devices. Altera recommends performing IBIS simulation to determine
that the overshoot and undershoot voltages are within the guidelines.
When using the Stratix IV device as a transmitter, you can use slow slew rate and
series termination to limit overshoot and undershoot at the I/O pins, but they are not
required. Transmission line effects that cause large voltage deviations at the receiver
are associated with an impedance mismatch between the driver and the transmission
lines. By matching the impedance of the driver to the characteristic impedance of the
transmission line, you can significantly reduce overshoot voltage. You can use a series
termination resistor placed physically close to the driver to match the total driver
impedance to the transmission line impedance. Stratix IV devices support series OCT
for all LVTTL and LVCMOS I/O standards in all I/O banks.
When using the Stratix IV device as a receiver, you can use a clamping diode (on-chip
or off-chip) to limit overshoot, though this is not required. Stratix IV devices provide
an optional on-chip PCI-clamping diode for column I/O pins. You can use this diode
to protect the I/O pins against overshoot voltage.
The 3.3-V I/O standard is supported using bank supply voltage (V_CCIO) at 3.0 V. In
this method, the clamping diode (on-chip or off-chip), when enabled, can sufficiently
clamp overshoot voltage to within the DC and AC input voltage specifications. The
clamped voltage can be expressed as the sum of the supply voltage (V_CCIO) and the
diode forward voltage.
f For more information about the absolute maximum rating and maximum allowed
overshoot during transitions, refer to the DC and Switching Characteristics for Stratix IV
Devices chapter.
External Memory Interfaces
In addition to the I/O registers in each IOE, Stratix IV devices also have dedicated
registers and phase-shift circuitry on all I/O banks for interfacing with external
memory interfaces.
f For more information about external memory interfaces, refer to the External Memory
Interfaces in Stratix IV Devices chapter.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1