EP4SE360F35I4 Datasheet, PDF (307/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Interface with the Use External PLL Option Enabled
8–27
Table 8–10. Signal Interface Between ALTPLL and ALTLVDS_TX and ALTLVDS_RX Megafunctions (Part 2 of 2)
From the ALTPLL
Megafunction
Parallel clock output (c2)
~(locked)
To the ALTLVDS Transmitter
To the ALTLVDS Receiver
Parallel clock used inside the transmitter core
logic in the FPGA fabric
—
rx_syncclock (parallel clock input) and
parallel clock used inside the receiver
core logic in the FPGA fabric
pll_areset (asynchronous PLL reset
port) ⁽²⁾
Notes to Table 8–10:
(1) The serial clock output (c0) can only drive tx_inclock on the ALTLVDS transmitter and rx_inclock on the ALTLVDS receiver. This clock
cannot drive the core logic.
(2) The pll_areset signal is automatically enabled for the LVDS receiver in external PLL mode. This signal does not exist for LVDS transmitter
instantiation when the external PLL option is enabled.
1 The rx_syncclock port is automatically enabled in an LVDS receiver in external PLL
mode. The Quartus II compiler errors out if this port is not connected, as shown in
Figure 8–21.
When generating the ALTPLL megafunction, the Left/Right PLL option is configured
to set up the PLL in LVDS mode. Figure 8–21 shows the connection between the
ALTPLL and ALTLVDS_TX and ALTLVDS_RX megafunctions.
Figure 8–21. LVDS Interface with the ALTPLL Megafunction ⁽¹⁾
FPGA Fabric
Transmitter Core Logic
tx_coreclk
LVDS Transmitter
(ALTLVDS)
tx_inclock
tx_in
tx_enable
rx_coreclk
Receiver Core Logic
LVDS Receiver
(ALTLVDS)
rx_inclock
rx_out
rx_enable
rx_syncclock
pll_areset
c0 ^ALTPLL
c1
inclk0
c2
pll_areset
locked
Note to Figure 8–21:
(1) Instantiation of pll_areset is optional for the ALTPLL instantiation.
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1