EP4SE360F35I4 Datasheet, PDF (122/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

5–6
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
Periphery Clock Networks
PCLK networks shown in Figure 5–5 through Figure 5–8 on page 5–8 are collections of
individual clock networks driven from the periphery of the Stratix IV device. Clock
outputs from the dynamic phase aligner (DPA) block, programmable logic device
(PLD)-transceiver interface clocks, I/O pins, and internal logic can drive the PCLK
networks.
PCLKs have higher skew when compared with GCLK and RCLK networks. You can
use PCLKs for general purpose routing to drive signals into and out of the Stratix IV
device.
Figure 5–5. PCLK Networks (EP4SGX70 and EP4SGX110 Devices)
CLK[12..15]
T1
PCLK[0..13]
CLK[0..3] L2
Q1 Q2
Q4 Q3
PCLK[42..56]
R2 CLK[8..11]
PCLK[14..27]
B1
CLK[4..7]
PCLK[28..41]
Stratix IV Device Handbook
Volume 1
September 2012 Altera Corporation