EP4SE360F35I4 Datasheet, PDF (248/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

7–24
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–19. Number of DQS/DQ Groups per Bank in EP4S100G3, EP4S100G4, and EP4S100G5 Devices in the 1932-Pin
FineLine BGA Package ⁽¹⁾, ⁽²⁾, ⁽³⁾, ⁽⁴⁾
DLL0
I/O Bank 1A
40 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 1C
19 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 2C
19 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 2B
13 User I/Os
x4=1
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 2A
39 User I/Os
x4=4
x8/x9=1
x16/x18=0
x32/x36=0
DLL1
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 3A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
EP4S100G3, EP4S100G4, and EP4S100G5 Devices
in the 1932-Pin FineLine BGA
I/O Bank 3B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 3C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 4C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 4B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL3
I/O Bank 6A
38 User I/Os
x4=3
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 6C
20 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 5C
17 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 5B
12 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 5A
40 User I/Os
x4=4
x8/x9=1
x16/x18=0
x32/x36=0
DLL2
Notes to Figure 7–19:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R_UP and R_DN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as R_UP and R_DN pins for OCT calibration. If two pins of a ×4 group are used as R_UP and R_DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
The DQS and DQSn pins are listed in the Stratix IV pin tables as DQSXY and DQSnXY,
respectively, where X indicates the DQS/DQ grouping number and Y indicates
whether the group is located on the top (T), bottom (B), left (L), or right (R) side of the
device. The DQS/DQ pin numbering is based on ×4 mode.
The corresponding DQ pins are marked as DQXY, where X indicates which DQS group
the pins belong to and Y indicates whether the group is located on the top (T), bottom
(B), left (L), or right (R) side of the device. For example, DQS1L indicates a DQS pin
located on the left side of the device. The DQ pins belonging to that group are shown
as DQ1L in the pin table. For more information, refer to Figure 7–20.
Stratix IV Device Handbook
Volume 1
February 2011 Altera Corporation