EP4SE360F35I4 Datasheet, PDF (419/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

February 2011
SIV51012-3.2
SIV51012-3.2
12. JTAG Boundary-Scan Testing in
Stratix IV Devices
The IEEE Std. 1149.1 boundary-scan test (BST) circuitry available in Stratix^® IV
devices provides a cost-effective and efficient way to test systems that contain devices
with tight lead spacing. Circuit boards with Altera and other IEEE Std.
1149.1-compliant devices can use EXTEST, SAMPLE/PRELOAD, and BYPASS modes to
create serial patterns that internally test the pin connections between devices and
check device operation.
This chapter describes how to use the IEEE Std. 1149.1 BST circuitry in Stratix IV
devices. The features are similar to Stratix III devices, unless stated otherwise in this
chapter.
This chapter contains the following sections:
■ “BST Architecture”
■ “BST Operation Control” on page 12–2
■ “I/O Voltage Support in a JTAG Chain” on page 12–4
■ “BST Circuitry” on page 12–4
■ “BSDL Support” on page 12–4
BST Architecture
A device operating in IEEE Std. 1149.1 BST mode uses four required pins, TDI, TDO,
TMS, TCK, and one optional pin, TRST. The TCK pin has an internal weak pull-down
resistor, while the TDI, TMS, and TRST pins have internal weak pull-up resistors. The
TDO output pin and all the JTAG input pins are powered by the 2.5-V/3.0-V V_CCPD
supply of I/O bank 1A. All user I/O pins are tri-stated during JTAG configuration.
f
For more information about the description and functionality of all JTAG pins,
registers used by the IEEE Std. 1149.1 BST circuitry, and the test access port (TAP)
controller, refer to the IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
chapter in volume 1 of the Stratix III Device Handbook.
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Stratix IV Device Handbook
Volume 1
February 2011
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