EP4SE360F35I4 Datasheet, PDF (77/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Design Considerations
3–21
Figure 3–18 shows sample functional waveforms of same-port read-during-write
behavior in old data mode for M9K and M144K blocks.
Figure 3–18. M9K and M144K Blocks Same-Port Read-During-Write: Old Data Mode
clk_a
address
rdena
wrena
bytenna
data_a
q_a (asyn)
A0
A1
01
10
00
11
A123
B456
C789
DDDD
EEEE
FFFF
A0 (old data) D_oldD_old23 B423
A1(old data) DDDD
EEEE
Mixed-Port Read-During-Write Mode
This mode applies to a RAM in simple or true dual-port mode that has one port
reading from and the other port writing to the same address location with the same
clock.
In this mode, you have two output choices if you use the output register: “old data,”
or “don’t care”. With MLABs, you also have the output register “new data.” In old
data mode, a read-during-write operation to different ports causes the RAM outputs
to reflect the “old data” at that address location. In don’t care mode, the same
operation results in a “don’t care” or “unknown” value on the RAM outputs.
f Read-during-write behavior is controlled with the RAM MegaWizard Plug-In
Manager. For more information, refer to the Internal Memory (RAM and ROM) User
Guide.
Figure 3–19 shows a sample functional waveform of mixed-port read-during-write
behavior for old data mode in MLABs.
Figure 3–19. MLABs Mixed-Port Read-During-Write: Old Data Mode
clk_a
wraddress
rdaddress
data_in
wrena
byteena_a
q_b(registered)
AAAA
A0
A0
BBBB
CCCC DDDD
A1
A1
EEEE
FFFF
11
01
10
A0 (old data) ^AAAA
11
01
10
AABB A1(old data) DDDD
DDEE
December 2011 Altera Corporation
Stratix IV Device Handbook
Volume 1