EP4SE360F35I4 Datasheet, PDF (301/432 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturlly advanced

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
8–21
■ Valid data is available two parallel clock cycles after the rising edge of
RX_CHANNEL_DATA_ALIGN.
Figure 8–15 shows receiver output (RX_OUT) after one bit slip pulse with the
deserialization factor set to 4.
Figure 8–15. Data Realignment Timing
rx_inclock
rx_in
rx_outclock
rx_channel_data_align
rx_out
32 10 32 10 32 10
3210
321x
xx21
0321
The data realignment circuit can have up to 11 bit-times of insertion before a rollover
occurs. The programmable bit rollover point can be from 1 to 11 bit-times,
independent of the deserialization factor. The programmable bit rollover point must
be set equal to or greater than the deserialization factor, allowing enough depth in the
word alignment circuit to slip through a full word. You can set the value of the bit
rollover point using the MegaWizard Plug-In Manager software. An optional status
port, RX_CDA_MAX, is available to the FPGA fabric from each channel to indicate when
the preset rollover point is reached.
Figure 8–16 shows a preset value of four bit-times before rollover occurs. The
rx_cda_max signal pulses for one rx_outclock cycle to indicate that rollover has
occurred.
Figure 8–16. Receiver Data Re-alignment Rollover
rx_inclock
rx_channel_data_align
rx_outclock
rx_cda_max
September 2012 Altera Corporation
Stratix IV Device Handbook
Volume 1